How to use Makefile

1. Writing a script file for compilation

Below is an example script file written to compile C files and Pro*c files.

#!/bin/ksh
# program compile
#


#main

        Param=$1
        case "$Param" in
                c)                      export COMP_TARGET=$2
                                        make -f Makefile.c;;
               pc)                      export COMP_TARGET=$2
                                        make -f Makefile.pc all;;
            clean)                      make -f Makefile.pc clean;;
                *)                      echo "Usage: $0 argument";;
        esac

2. Writing a Makefile

Below is an example Makefile written to compile a C file.

<Makefile.c>

# Server makefile
TARGET  = $(COMP_TARGET)
APOBJS  = $(TARGET).o
LIBS    = -laps
OBJS    = $(APOBJS) $(SDLOBJ) $(SVCTOBJ)
SVCTOBJ = $(TARGET)_svctab.o
CFLAGS  = -O -I$(WEBTOBDIR)
APPDIR  = $(WEBTOBDIR)/ap
SVCTDIR = $(WEBTOBDIR)/svct
LIBDIR  = $(WEBTOBDIR)/lib
.SUFFIXES : .c
.c.o:
        $(CC) $(CFLAGS) -c $<
$(TARGET): $(OBJS)
        $(CC) $(CFLAGS) -L$(LIBDIR) -o $(TARGET) $(OBJS) $(LIBS)
rm -f $(OBJS)
$(APOBJS): $(TARGET).c
        $(CC) $(CFLAGS) -c $(TARGET).c
$(SVCTOBJ):
        touch $(SVCTDIR)/$(TARGET)_svctab.c
        $(CC) $(CFLAGS) -c $(SVCTDIR)/$(TARGET)_svctab.c
clean:
        -rm -f *.o core $(TARGET)

Here’s how to compile the Makefile:

$compile c “C file name without extention”